FPGAs in C with Cynth

Programming an FPGA with Verilog looks a lot like programming. But it isn’t, at least not in the traditional sense. There have been several systems that aim to take C code and convert it into a hardware description language. One of these, cynth, is simple to use and available on GitHub. You will need to install scala and a build system called sbt, if you want to try it.

There are limitations, of course. If you want a preprocessor, you’ll have to run it separately. You can’t use global variables, multiplication, floats, and many other pieces of C. The compiler generates a Verilog file for each C function.

A traditional C program executes one thing at a time unless you use special techniques on a multiprocessor. Even then, there is some practical limit to how many CPUs you will likely control. An FPGA, on the other hand, allows you to implement things that occur in parallel. For example, consider this:

while (1)
   {
     out1=ctr1++;
     out2=ctr2++;
   }

The out1 value is going to change a little bit before the value in out2. If you had a bunch of these, say up to out999, the delay could be significant. Equivalent Verilog code might look like:

always @(posedge clk)
begin
   out1<=ctr1;
   ctr1<=ctr1+1;
   out2<=ctr2;
   ctr2<=ctr2+1;
end

This looks almost the same, but the outputs will change at the same time no matter how many there are. What’s more is that all the other things you can’t see will also happen at the same time. Just like a hardware AND gate doesn’t “scan” its inputs, an FPGA processes all of its inputs and generates outputs.

In the case of cynth, each C function creates a Verilog module that has the same arguments as the function along with another argument to stand in for the return value, if any. There will also be inputs for the system clock, a reset signal, and three control signals. One is an input that enables the processing. There are two outputs. One indicates the function is available to enable and another indicates a result is available.

The example provided with the code is a Cylon eye pattern that drives four LEDs. There are two external functions that are created with pure Verilog. The write_leds function drives the LEDs and a sleep function produces a delay.

The C code is a straightforward function named roving:

 while (1)
 {
 if (dir && c == 8)
 dir = 0;
 else if (!dir && c == 1)
 dir = 1;
 
 if (dir)
 c <<= 1;
 else
 c >>= 1;
 
 write_leds(c);
 
 sleep(1000); // 1s
 }

The corresponding Verilog files perform the same function as you can verify using a Verilog emulator.

If you want to dig into the generated code, you can find out more about Verilog with some projects. If C isn’t your thing, you could always try Python.

Filed under: FPGA