Visualizing Verilog Simulation

You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation. You might get some printed information or you might get a graphical result by dumping a waveform, but you don’t usually see the circuit. A new site combines Yosys and a Javascript-based logic simulator to let you visualize and simulate Verilog in your browser. It is a work in progress on GitHub, so you might find a few hiccups like we did, but it is still an impressive piece of work.

If you aren’t up on Verilog, you can use the “Load Example Code” button to pick a few samples. You might try this if you want something really simple:

module test(
input a,
output b
);

assign b=~a;

endmodule

That creates a circuit like this:

The A button is live, so clicking it will change the little faux LED to red along with the associated wires. It may not be obvious, but you can drag components around to suit you. You can also delete wires and create new connections. If there is a way to add and delete components, we couldn’t figure it out.

This isn’t a bad way to learn Verilog since you can quickly see what the code is doing. It isn’t flexible enough to be a workhorse simulator, though. For example, naming something clk puts a clock input on the schematic, but using any other name as a clock leaves it as a button like “a” in the example above. There’s no way to set the clock either.

This is fun, though. Yosys has a lot of features we usually don’t use, including the ability to generate graphviz files with schematics of the design, although they aren’t as clear as this. We’d love to see this married with Falstad as the simulation engine so you could basically use Verilog modules as part of your simulation. That simulator can do digital circuits, it just doesn’t accept Verilog.  If you want real simulation in your browser, try EDA Playground, which we use a lot.