FPGA used VHDL for Fractals

Over on GitHub, [ttsiodras] wanted to learn VHDL. So he started with an algorithm to do Mandelbrot sets and moved it to an FPGA. Because of the speed, he was able to accomplish real-time zooming. You can see a video of the results, below.

The FPGA board is a ZestSC1 that has a relatively old Xilinx Spartan 3 chip onboard. Still, it is plenty powerful enough for a task like this.

The project doesn’t directly drive a display. It does the math, stores the results in the board’s onboard RAM and then sends a frame to the PC using the ZestSC1’s USB port. Currently, the code isn’t pipelined and a future task is to add pipelining so that it computes a new pixel on each clock cycle, after some latency, of course.

The repo contains the VHDL code and some C++ code that interfaces with the board and displays the results. If you have that particular board, it would be a good basis for a different project.

Our FPGA boot camps use Verilog, but they are still a good place to start if you want to learn FPGAs. The concepts still apply and the recently added module on state machines will give you a good head start no matter what language you use. If you crave more VHDL math, there’s always CORDIC.